Efficient Analysis and Optimization of ESD Protection Circuits

Electrostatic Discharge (ESD) is generally recognized as an increasingly important issue for modern integrated circuits. Thinner gate oxides, complex chips with multiple power supplies and/or mixed-signal blocks, larger chip capacitance and faster circuit operation all contribute to increased ESD-sensitivity of advanced semiconductor products [1]. Detailed understanding of complex circuit-device interactions is essential for the design of effective ESD protection. This paper presents results of an ESD failure analysis, where excessive distance between the IO pad and the power supply ESD protection can lead to permanent failure during ESD stress. The critical distance for a given protection type is calculated and remedies for the situation shown. Industrial ESD Analysis Although it has been long expected that simulation can and should serve a big role in addressing ESD issues, industrial applications have been rare. The problem has been approached from two directions: circuit simulation with added empirical high-current device models [2] and device simulation with added mixed-mode simulation. The circuit simulation approach has suffered from its non-physical nature and poor convergence. The device simulation approach has been previously limited to few research-type aplications because of ease-of-use problems, meshing issues and excessive simulation run times. This paper discusses an industrial application of a novel ESD simulation tool [3], which combines physical acuracy of mixed-mode circuit-device simulation with the usability of an integrated circuit designer package. The tool provides capabilities for in-depth studies of device-level effects [4],[5] as well as analyses of larger circuits characterized by complex interactions within I/O buffer circuits embedded in their chip environments and Charged Device Model (CDM) problems [6]. Numerical analysis of industrial ESD problems poses a number of specific challenges. ESD events push circuits into high voltage and high current operation regimes posing challenges for convegence, their high speed makes the incorporation of RLC parasitics important, and the distributed nature of many discharge events necessitates the inclusion of a substantial number of active and passive elements. Ease-of-use is a critical consideration for the acceptance of ESD tools, since ESD problems are typically addressed by design engineers and not a dedicated research group. Device synthesis and automatic mesh generation are used in conjunction with inverse modeling to generate devices which assure accuracy and reasonable simulation times. These calibrated devices are stored in a library to be used by ESD circuit designers. The ESD-relevant circuit is specified through the built-in schematic capture tool, finite-element device models are imported from the device library. IO Buffer and ESD Protection The simulated ESD-relevant circuit is shown in Fig. 1 along with the device structure and mesh used for the protection clamp (insert). The mixed-mode circuit contains five active finite-element level devices (3 NMOS and 2 PMOS) as well as passive circuit elements. MOSFET widths are specified as in the layout (input CMOS pair with Wn/Wp=40μm/ 20μm, wider output MOSFETs Wn/Wp=200μm/100μm and a power supply clamp with Wn=400μm). A chip capacitance of 200pF and intrinsic Vdd and Vss resistances of 5Ω each are also included since both have a significant effect on circuit behavior during ESD stress. An HBM discharge circuit is included with a 100pF capacitor pre-charged to 2kV, 7.5μH inductor and 1.5kΩ resistor. MOSFET breakdown behavior was compared to experimental data. Simulated curves shown in Fig. 2 demonstrate snapback for NMOS devices with triggering voltages around 9.5V. The P-MOSFET triggers at around 11V but does not enter snapback. This behavior corresponds to experimental data. Figures 3, 4, 5 show currents versus time for the clamp current AM2 (Fig. 3), output buffer current AM9 (Fig. 4) and chip current AM7 (Fig. 5) for three different R6, R7 values: 1Ω,2Ω,4Ω. These resistors represent the electrical distance between the IO pad and power supply protection clamp M10 (Fig. 1). A qualitative transition is seen between the values 2Ω and 4Ω. For 2Ω or smaller the entire HBM pulse is absorbed by the ESD protection device M10, while for 4Ω and larger the output buffer NMOS M13 triggers first and draws a current of about 0.17A. This current is high enough to destroy the IO buffer power supply tracks. In cases when the output buffer NMOS triggers, a delay is visible in the triggering of the clamp M10 as shown in Fig. 3. The chip capacitor current AM7 displays a characteristic negative spike (Fig. 5) when the clamp finally triggers. Lowering the Clamp Triggering Voltage An obvious solution to this ESD problem is to reduce the resistance between the IO pad and clamp. Another solution which may be preferable is to lower the triggering voltage of the protection clamp. One common technique to achieve this has been proposed in [7],[8]. It involves the addition of a capacitor between gate and drain of the clamp to raise the gate potential temporarily during the pulse. A drawback of this technique is the need to carefully optimize the circuit parameters to cover all relevant ESD discharge types. Simulation is an efficient tool for this task. Our modified circuit is shown in Fig. 6. The added capacitor C2 and resistor R13 transform the ESD clamp M10 into a lowpass filter with an RC constant of about 7ns. The gatesource voltage of the clamp M10 rises above the MOSFET’s threshold voltage (Fig. 7) causing the clamp to conduct. This is long enough to allow the clamp to trigger well before the output buffer reaches its triggering voltage of about 9.5V and thereby force the voltage across the protection clamp to at a safe low value (Fig. 8). As shown in Fig. 9, the addition of capacitor C2 causes the clamp to conduct current early on. This fully protects the output buffer, which now does not trigger (Fig. 10) despite the large 4Ω resistance between IO pad and ESD clamp. The robustness of the protection scheme is thus increased allowing more flexibility in the placement of protection clamps.